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Lattice Semiconductor
CSIX Level 1 IP Core User’s Guide
network element to pause transmission on the inbound data path, thereby preventing the inbound FIFO from over-
?owing.
The fourth ?ow control mechanism is associated with the outbound FIFOs. If either of the associated “near-full” sig-
nals is asserted, the inbound path deasserts the local control/data ready signal. This should signal the user appli-
cation or remote CSIX element to pause transmission on the outbound path, thereby preventing the outbound
FIFOs from over?owing.
Port Aggregation
The core supports port aggregation. If an application instantiates more than one 32-bit CSIX core, two or more
cores can be aggregated into a larger CSIX interface. For example, two cores can be aggregated to operate as a
64-bit CSIX interface, three cores can operate as a 96-bit interface, and four cores can operate as a 128-bit inter-
face. Proper operation of the port aggregation mode requires that the external CSIX ports conform to the clock
domain skew limits listed in the CSIX-L1 Speci?cation. Also, the internal user application for the CSIX core must
use a single timing domain to clock the aggregated cores.
Three user parameters control the con?guration of port aggregation:
1. Port_Aggregation (yes, no)
2. Aggregation_Span_0 (2,3,4)
3. Aggregation_Span_1 (0,2)
If port aggregation is to be instantiated, then the ?rst parameter must be yes. If aggregation is instantiated, then the
last two parameters must be speci?ed. Typically, only one aggregation function will be speci?ed (Span_0). How-
ever, if four cores are instantiated for an application, it is possible to create two 64-bit CSIX interfaces. In this case
Span_0 = 2, and Span_1 = 2. The highest numbered core is always the most signi?cant 32-bit group of the aggre-
gate. The other cores decrease in precedence, down to core 0 as the least signi?cant group.
Register Interface
A bank of registers is implemented to manage various programmable control functions and store various error and
status signals. These registers are controlled by a register interface that is compatible with the ORCA system bus
interface as shown in Figure 1. When a user instantiates an ORCA ? SYSBUS slave interface to control the core
registers, the external FPGA control interface is compatible with a Motorola MPC860 Power PC interface. The
description below is speci?c to this IP core. Therefore, the bus widths may not match the generic bus widths shown
in Figure 1.
The core maintains an 8-bit implementation of the system bus. A 9-bit address bus (us_addr[8:0]) speci?es the
locations of the registers (0x000 - 0x1FF). An active low us_ready signal enables a register access cycle. An
us_wr signal enables writing when high, reading when low. Data to be written to registers appears on the 8-bit bus
“us_wdata[7:0]”. Data read from registers appears on the 8-bit bus “us_rdata[7:0]”, and is driven only during access
to one of the implemented registers. The us_clk signal synchronizes register accesses and can be any frequency
up to 50MHz. The active high us_ack signal asserts when the core is ready to end the current bus cycle.
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相关代理商/技术参数
CSIX-PI40-O4-N1 功能描述:输入/输出控制器接口集成电路 CSIX to PI40 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
CSJ-100 制造商:GREENLEE TOOL CO 功能描述:Digital Open Jaw Clampmeter 制造商:Greenlee Textron Inc 功能描述:CLAMPMETER
CSJ-23 功能描述:EXTRACTION TOOL FOR SCS RoHS:否 类别:工具 >> 插入，抽取 系列:* 标准包装:1 系列:* 其它名称:0011-03-00080011-03-0008-E00110300080011030008-E11-03-0008-E1103000811030008-EQ4729393AT0980176A
CSJ32C1 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C3 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C5 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E1 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E3 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals